Connecting Steps Together

There are two ways to connect two steps in a graph (i.e., to draw edges between nodes):

  1. With Graph.connect_by_name()
  2. With Graph.connect(), Step.o(), and Step.i()

Graph.connect_by_name() tries to automatically connect outputs of one step to inputs of the other step if the files have the same name. Multiple edges can be drawn with a single call.

Graph.connect() explicitly connects a single output of a step (specified by Step.o()) to a single input of another step (specified by Step.i()). Only a single edge is drawn.

Graph building is generally cleaner when connecting by name. The more explicit connect API is useful when names do not match and it is inconvenient to adjust step configurations to make them match.

Automatic Connection by Name

Here is a simple graph with two nodes, one for the design RTL and the other which runs synthesis. We would like to connect the design RTL to the synthesis node.

g = Graph()

rtl = Step( ...  get rtl  ... )
dc  = Step( ... get synth ... )

g.add_step( rtl )
g.add_step( dc  )

The RTL node has an output “design.v” and the synthesis node takes an input “design.v”. Since these names match, we can use Graph.connect_by_name() to simply connect these nodes with an edge like this:

g.connect_by_name( rtl, dc )

We get this graph with automatic connection:


Explicit Connections

Here is another simple graph with the same two nodes for design RTL and for synthesis. However, the names no longer match. We would still like to make this connection.


We want to connect the RTL node’s output “GcdUnit.v” to the synthesis node’s input “design.v”. Since these names do not match, connecting by name will not automatically draw any edges.

We can connect explicitly using Graph.connect(), Step.o(), and Step.i():

g.connect( rtl.o( 'GcdUnit.v' ), dc.i( 'design.v' ) )

We can read this clearly: Connect rtl output “GcdUnit.v” to dc input “design.v”.

Step.o() and Step.i() are helper methods necessary for differentiating outputs from inputs within a step. For example, the synthesis node has an input file “design.v” (i.e., the RTL design) and also an output file “design.v” (i.e., the synthesized netlist) with the same name.

We get this graph with our explicit connection: